Flip Chip Processing for SIP Applications

February 1, 2004
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System-in-packaging (SIP) allows designers to tailor high-density and high-performance electronic systems into application-specific packages at costs less than custom system on chip solutions. Depending on their application environment, SIPs provide high levels of integration between interconnect levels, passive elements, optoelectronic, digital and radio frequency functions. SIPs can be used to assemble application-specific integrated circuits, memory, digital signal processors and radio frequency devices in stacked die and flip chip configurations. SIPs can contain integrated passive structures, including resistors, capacitors and inductors. Emerging SIPs may also include integrated, optical waveguide interconnects, micro-optoelectromechanical systems and microelectromechanical systems and components.

Flip chip technology has emerged as the best way to manufacture system in package applications. Flip chips are an advanced form of surface mount technology in which bare semiconductor chips are turned upside down and bonded directly to a printed circuit board or chip carrier substrate.

The chip can be made of silicon, gallium-arsenide, indium-phosphide or silicon-germanium. The substrates could be ceramic, epoxy-glass laminate, polymer thin-film, resin-coated copper, glass, silicon, dielectric-coated metal, liquid crystal polymer, metal matrix composite, low-temperature co-fired ceramic, ceramic thick-film and multilayer high temperature co-fired ceramic.

Interconnection between the chip I/O and substrate is achieved using a bump structure on the chip and a bonding material-typically on the substrate. The bumps can be solder or a conductive adhesive.

Solder bump flip chip interconnections were developed to eliminate the expense, unreliability and low productivity of manual wire bonding. In contrast to wire bonding, the flip chip allows all I/Os to be connected simultaneously.

Like its predecessors, flip chip technology was initially applied to peripheral contacts, but it quickly progressed to area arrays. This allows for high I/O counts at large pitches and reduced die size because solder bumps can be put over the entire active device area.



Design Guidelines

When designing flip chips for SIP modules, engineers must consider I/O layout, solder mask design, pad shape and bond pad metallization.

The most influential variable in how the bond pads are designed is the number of chip I/Os and whether they are a perimeter array or a full area array. Because perimeter array devices have a limited number of I/O, it is easier to route out the I/O of these chips. The I/O of full area array devices are usually at larger pitches. However, once they have more than 50 I/O at a pitch below 12 mils, the board complexity dramatically increases because interior balls can't be routed out on the top layer of the board.

For perimeter devices, the I/O design will drastically affect board cost. If the pitch gets below 8 mils, quality may suffer if the boards are made in large quantities. Once trace conductor line and space dimensions go below 4 mils, the number of board houses qualified to fabricate this level of technology decreases.

The most common board-fabrication defects are caused by overetching the metallization or unacceptible solder mask registration. By designing failsafe mechanisms into the bond pad layout, the yields for SIP substrates will increase.

To control solder mask registration and ensure that the entire bond pad will be exposed for solder attachment, a 2- mil separation distance around the bond pad is recommended. This allows for up to 2 mils of solder mask movement around the metallized region. This rule can be applied to both metal, mask or hybrid bond pad designs.

The solder mask height should not interfere with the placement of the solder ball on the surface of the metallized bond pad. Enough solder mask X-Y spacing should be allowed for the ball to sit inside of the mask opening around the pad. Also, the mask space between two openings should not fall below 2 mils. Anything below 2 mils will be hard to process. Solder bridging could also occur.

Unfortunately, with every design choice, there is a drawback. As the number of solder mask keep-out areas increases, the risk of creating capture voids in the solder mask openings increases. This is caused by underfill flowing too quickly over the gaps between the solder mask opening and the bond pad. This traps air bubbles. Usually, this is corrected by process development and can be reduced by choosing slower-flowing underfills or changing underfill flow directions.

Pad shape is another variable to consider when designing flip chip-based SIP modules. Pad shape does not affect the chip yield. In fact, as long as there is an exposed, clean, wettable surface touching the solder during its liquidous state, solder interconnection should not fail. One good reason to change pad shape is for solder nonwetting inspection. When using a square or rectangular bond pad design on a circular ball, reflow will cause the ball to appear elliptical, making it easier to identify post-reflow nonwetting.

Bond pad metallization is also a key area when designing flip chip SIPs. Typically, excessive noncoplanarity of the bond pad or solder ball heights will affect chip I/O yield. To minimize the effects of coplanarity-related problems, pad surface finishes are normally not used for flip chips. If a surface finish must be used, the most common are copper-electroless nickel-immersion gold and copper organic solder preservative. However, there are many different choices when deciding on a surface finish. And any finish choice can be at risk of surface contamination or an incorrect metallization deposition defect, such as poor plating, over-etching or black pad oxidation.

SIP modules are small and use as much space as possible. Proximity of other chips or devices adjacent to the flip chip will directly affect the process. When designing flip chips, a keep-out area around the chip for underfill processing should be considered. At least 2 millimeters of space should be left around the flip chip edge. This allows for underfill flow and filleting. And because a slightly larger area is needed on the side of underfill dispensing, 2.5 to 3 millimeters is recommended.



Under Bump Metallization

Under bump metallization (UBM) serves as a compatible layer between the bump metallization and final chip metallization. The most common final chip metallization is aluminum. Gold is also used, mainly for gallium-arsenide applications. And copper is gaining in popularity due to its improved electrical performance. The UBM also helps prevent corrosion of the chip metallization due to diffusion of contaminant ionics from the encapsulants and environment.

The structure of the UBM consists of an adhesion layer covering the chip metallization, a barrier layer, a wetting layer and an anti-oxidation barrier. The adhesion layer promotes a strong interface between the bump, the chip metallization, chip passivation, and any dielectric passivation. Chip passivation provides protection from the environment, insulates the devices on the silicon surface and acts as a buffer layer for stress relief. Careful material selection is necessary to provide good adhesion between these diverse surfaces. Typical adhesion layer materials are chromium, titanium, nickel, tungsten, titanium-tungsten and zincate.

The purpose of the barrier layer is to prevent diffusion of metal species and ionic contaminants into the chip metallization and adhesion layer. Diffusion can result in the formation of brittle intermetallics and corrosion of the chip-adhesion metallization, which could significantly lower the reliability of the interconnect system. Common metallurgies used for barrier layers include chromium, tungsten, titanium, titanium-tungsten, nickel and chromium-copper.

After the barrier layer, there is a wetting layer. This metallization provides a consumable layer for the subsequent bump metallization to wet and react with, forming intermetallics. Molecular diffusion of reactive bump species into the wetting layer is common. This often results in intermetallic compounds being formed.

The final UBM layer is an anti-oxidation barrier, which is optional. It is typically a very thin layer of gold. Thin layers of gold are used, because gold will not embrittle the UBM-bump interface due to the formation of intermetallics.

In general, UBM selection must be based on the desired bump metallization, the operating conditions of the chip, current-carrying requirements and the overall assembly process history required (i.e., multiple reflow cycles).

UBM is necessary for several reasons. Chip passivation is necessary to protect the aluminum metallized chip from moisture and corrosion. A polyimide layer is then applied for stress relaxation. The first metal layer is the adhesion layer. This metal must adhere to both the aluminum oxide and the polyimide. It must also have low electrical contact resistance. Often, argon sputter etching of the aluminum surface is used to remove aluminum oxide and reduce interfacial resistance. The second layer is the barrier layer. This layer prevents the solder from migrating too quickly and corroding the aluminum device or dewetting the chromium layer during multiple reflows. Traditionally, a chrome-copper alloy has been used as barrier layer. The third layer is the wetting layer. This layer, usually a thick layer of copper, is necessary because the solder will not wet the metal deposited for the barrier layer or bare aluminum. Finally, a flash of gold is placed on the top of the wetting layer to inhibit copper oxidation in a dual evaporation process.

In general, these metallization steps are completed in a clean, large vacuum environment. In addition to the metal layers, an underfill-usually silica-filled epoxy-is applied between the joined chip and substrate. This underfill is completed after the solder is reflowed. Any rework and repair must be done before the underfill. The underfill is needed to improve reliability. Because there is a mismatch in the coefficients of thermal expansion among the chip, the solder interconnects and the substrate, stresses will occur. The underfill distributes the thermomechanical stresses over a larger area, significantly increasing reliability.



Bump Materials

The bumps in a flip chip provide four functions: electrical connection between the chip and the substrate; a heat dissipation path from the chip; environmental protection; and a structural link between the chip and the substrate. The materials and processes involved in the manufacture of the flip chip interconnect system determine its performance.

The most common materials used for bumping flip chips include solder, metallic stud bumps and compliant polymer bumps. Solders can be divided into three primary materials:

n high temperature with melting points in excess of 250 C.

n moderate temperature with melting points between 200 and 250 C.

n low temperature with melting points less then 200 C.

Solder bumps are deposited onto the UBM using several processes. Evaporation was the earliest process. It was developed by IBM for its flip chip technology. It is still commonly used today and requires a physical mask, typically molybdenum, that is aligned to the wafer I/O pads and released after deposition. The mask must have a draft angle through the apertures for the solder to be released from the mask.

A second process for deposition of solder is electroplating. The solder is electroplated through a polymer photoresist mask to control volume and registration. The bumps are reflowed after plating to homogenize the solder microstructure, because the electroplated solder is phase-separated on deposition.

A third process for solder deposition is printing. Squeegee printing specially designed solder paste can be accomplished using a precision stencil and automated printers. At pitches less than 250 microns, this process becomes more difficult. Bump printing can also be achieved using a polymer photoresist mask. However, the solder is doctor-bladed or squeegeed into the holes in the resist. A third printing process is based on ink-jet printing technology. In this case, molten solder drops are jetted onto the bond pads forming the bumps. Solder jet printers can be configured for drop-on-demand deposition or continuous drop deposition.

Stud bumps can be plated or deposited using a wire stud bumping technique. Plated stud bumps are derived from the systems used for tape automated bonding (TAB), including gold, nickel, copper, gold-tin, nickel-gold, and nickel-copper. Both electrolytic and electroless plating techniques can be used, and they are significantly faster than wire stud bumping. Wire stud bumps are formed using a ball-bonding technique. The wire is fractured after ball bond formation. The wire stud bumps can be coined to form a uniform structure for bonding. The most common wire stud bumps are made with 25-micron-diameter gold wire.

Compliant polymer bumps have several configurations. The most common consist of a polymer elastomer filled with conductive metal particles, which is then over-coated with gold. Conductive polymer bumps are most often screen- or stencil-printed onto the wafer I/O pads metallized on a UBM. The gold overcoat is based on electroless or immersion gold plating.



Interconnect Materials and Processing

Bonding the bump to the substrate metallization is achieved using a material that provides an electrical and mechanical connection. Often, the bump and bond materials are the same, or the bond and encapsulant materials are the same.

For solder interconnect systems, the bond can consist of three basic types. The first is a fully wetted, controlled-collapse solder interconnect. The entire solder bump is raised above its liquidous temperature, wets and reacts with the substrate metallization.

Although not used commercially, the second solder interconnect system is a solid-state bond between the bump and substrate metallization. Solid-state bonds are commonly formed using thermocompression or thermosonic bonding techniques-much like wire bonds or TAB. In this case, the interconnects are gang-bonded so that all interconnections are formed simultaneously.

The third solder interconnect structure consists of a cap reflow configuration. In this case, a high melting point bump is bonded to the substrate trace with a lower melting point alloy. The most common configuration is a high-lead solder bump bonded with a eutectic solder cap that is plated on the substrate trace.

During reflow, the eutectic solder will liquify, wet and react with the substrate metallization and high lead bump, forming a robust interconnection with a known standoff height controlled by the bump height. This interconnect configuration is commonly used in flip chip package applications for microprocessors and application-specific integrated circuits.

Conductive adhesives are also used for bonding flip chips to the substrate metallization. There are two basic types: isotropic and anisotropic.

Isotropic conductive adhesives are typically thermosetting polymers filled with conductive particles. The most common material is epoxy filled with silver flakes. They are conductive in all directions upon cure, yielding an electrically functional interconnect. Isotropic adhesives can be printed onto the substrate bond pads, printed on the chip bumps or dip-transferred to the bumps. In the latter case, the bumped chips are dipped in a precision thin-film of the conductive paste, transferring a controlled amount of the adhesive onto the bumps. Upon assembly, the conductive adhesive forms a bond between the bump and substrate metallization. The most common bumps used for these interconnects are gold wire and gold-plated stud bumps. Gold surface metallization on the substrate traces is used to minimize corrosion on the interconnect systems. These materials form a mechanical contact rather than a metallurgical bond. The electrical performance of the mechanical contacts is adequate for many applications, but can be problematic under conditions where corrosion can occur. In general, unless pinhole-free noble metal finishes are used over the bumps and substrate metallization, the electrical contact resistance between the bump and the substrate metallization can increase over time.

Isotropic conductive adhesives do not self-align during assembly like solders. Therefore, they require high-precision assembly processes that are slower and more costly than soldering processes. They are commonly used for flip chip on glass assembly for flat panel display production. If the substrate tends to warp during assembly, particularly during cure, conductive adhesive interconnects require the chip to be held under force to tack cure the adhesive. The underfill can then be applied to the flip chip and simultaneously cured with the conductive adhesive. Without tack curing the conductive adhesive, any warpage of the substrate or chip can cause the interconnect to fail, because it is brittle prior to complete cure.

Anisotropic conductive adhesives can be film or paste polymer materials filled with conductive spheres. The conductive spheres can be metal-nickel or gold-coated nickel-or metal-coated polymer-gold-coated or nickel-gold coated. In the latter case, both solder and hollow polymer spheres are used. Anisotropic conductive adhesives do not conduct electric current until compressed to the point where the conductive spheres are compressed and captured between the bump and substrate trace. Similar to isotropic conductive adhesives, bumps and substrate metallization are typically noble metals to minimize corrosion failures. Assembling flip chips with anisotropic conductive adhesives requires high-accuracy placement. The materials do not self-align like solders. In addition, anisotropic conductive adhesives require relatively high bonding forces to make good electrical contact. The assembly process involves high-accuracy placement using a flip chip bonder followed by a high-force bonding tool having a high degree of planarity between the bonding head and the substrate holder. Typical bonding forces are 20 to 100 grams per bump, which limits I/O counts of the chips that can be assembled.



Underfill Material Selection

Underfill encapsulants are applied at the interface between the chip and substrate. They compensate for the differences in coefficients of thermal expansion (CTE) between chip and substrate. For example, the CTE of a silicon flip chip is approximately 3 parts per million per degree Celcius (ppm/C). In contrast, an FR4 organic substrate has a CTE of 17 to 22 ppm/C. An alumina ceramic substrate has a CTE of approximately 7 ppm/C, resulting in significantly lower thermomechanical stresses on the interconnects. For relatively small flip chip components mounted on ceramic substrates, underfill materials are not used.

One of the primary purposes of underfill is to couple the substrate over the entire area of the chip, or at least around its perimeter, lowering the effective thermomechanical stress on the flip chip interconnects. By coupling the chip and substrate, the effective composite CTE falls between the chip and substrate, increasing reliability. The effectiveness of underfills depends on the relative difference in CTE between the chip and substrate. Flip chips on ceramic substrates with underfill are more reliable than flip chips on organic substrates with underfill.

Underfills can also protect the interconnect from environmental effects and absorb harmful alpha particle emission from the lead in solders, which can cause soft errors in logic circuits.

The underfill is applied after interconnection. A filled liquid polymer is dispensed along a single edge or two adjacent edges of the flip chip. Surface tension draws the material under the chip and through the interconnect geometry. Additional material may need to be applied to completely fill the area beneath the chip.

After dispensing, the underfill is cured in an oven. Typical cure temperatures for underfill range from 130 to 175 C.

In addition to capillary flow, underfills can also be pre-applied on the substrate prior to chip assembly and compressed during chip assembly. Another underfill process involves injecting the viscous polymers under the chip using a transfer molding process or discrete injection process.

Underfill encapsulants are typically silica-filled epoxies. Short fill and cure times are essential for cost-effective and high-volume manufacturing. Materials should provide mechanical shock and bending protection, as well as a barrier for environmental protection. Epoxies cured with anhydride exhibit a high glass transition temperature, good chemical resistance, low moisture absorption, good flow properties and good adhesion strength to other packaging materials.

The most critical properties of underfills are the CTE, glass transition temperature, pot life, viscosity, filler size, alpha particle emission and extractable ionics. Typical viscosities for underfill materials at room temperature range anywhere from 10,000 to 30,000 centipoise at low shear rates. Flow rate during processing depends on such factors as viscosity, temperature, surface tension, gel time, gap height and surface wettability.

Process parameters associated with capillary flow are the dispensing pattern, amount of material, temperature, dispensing needle speed and the distance between the material and the chip. Material can be applied in one of two patterns. Material can be dispensed along one edge of the chip. Once the material has flowed underneath the chip, dispensing on the remaining sides will guarantee complete coverage and fillet formation. The other method is to dispense material along two adjacent chip edges. This is typically referred to as L-shape dispensing. Increasing board and chip temperature will aid the flow of the underfill.

Potential underfill problems include voiding, delamination and moisture penetration. Voids can be caused by air pockets forming between the chip and the substrate during the dispensing process. Delamination can occur due to poor wettability and adhesion of the underfill material. Voiding and delamination typically lead to solder cracking and moisture penetration. Underfill segregation is another type of problem. It happens when filler particle additives in the underfill group together under the chip. This causes differences in underfill density and affects the stress distribution under the die. These types of defects are process- and material-related. With correct underfill process development, they can be drastically reduced or eliminated.

This paper was presented at APEX 2003 in Anaheim, CA.

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