Low-voltage components are difficult to accurately, reliably and safely test using conventional in-circuit testers.

Low-voltage electronic devices have enabled engineers to design products with lower power consumption requirements, reduced cooling requirements, and faster processing speeds. These benefits have made it possible for the performance of the PC to increase over 400-fold in the past 18 years, even though the energy consumed by the PC has remained largely unchanged.

For years, 5 volts VCC had been the standard for both core and memory logic. However, as application-specific integrated circuits (ASICs), microprocessors and digital signal processors have increased in complexity and functionality, that standard has changed. Modern processes for manufacturing complimentary metal oxide semiconductors (CMOS) produce smaller structures, in which the gate oxide thickness of each transistor is sensitive to electrostatic field strength. Because field strength is proportional to supply voltage, the supply voltage must be reduced for reliable operation of the smaller structures.

Put another way, making electronic devices more complex, without enlarging the overall size of the chip area, requires reducing the structure size, which also requires reducing the VCC power supply voltage. With a structure size of 0.6 micron, the limit for reliable operation is less than 5 volts. With a structure size of 0.35 micron, the limit is 2.5 volts.

If manufacturers are not assembling low-voltage devices today, they will be tomorrow. Logic voltage thresholds for ICs have steadily declined over the past decade, and they will continue to do so. For example, the logic voltage thresholds for ICs made by Texas Instruments have gradually decreased from 5 volts to 2.5 volts to 0.8 volt.

Testing Low-Voltage Devices

In-circuit testers (ICTs) rely on bed-of-nails fixtures to gain electrical access to every node (or net) of the printed circuit board (PCB). Using this access, ICTs take a "divide-and-conquer" approach, testing each component as if it were the only one on the PCB. If all the components pass, then the board is likely free of assembly faults and will function correctly. This test strategy is possible because ICTs use techniques like "disable" and "inhibit" to isolate the component being tested from the unwanted electrical effects of surrounding components.

To perform powered-up vector testing of digital components, ICTs use driver/sensor (D/S) pins. These pins drive the input pins to the required logic states and sense the resulting logic states of the output pins. The digital pin drivers are low-impedance current sources that can source or sink 600 milliamperes or more. This current source momentarily forces nodes on the board to the logic levels required by the test. This technique of temporarily overdriving component outputs to force a node to its opposite logic state is commonly referred to as backdriving.

These powered-up vector testing techniques have been used successfully by ICTs for more than 20 years. However, today's low-voltage devices are increasingly difficult to accurately, reliably and safely test using conventional ICTs. The reasons for this are related to the inaccuracy of conventional D/S pin designs, and the greater likelihood of violating the strict maximum voltage and current specifications of low-voltage devices.

To successfully test low-voltage devices, the driver pins must be accurate enough to supply the logic-high and logic-low voltages that are expected by the devices' input pins. Likewise, the sensor pins must be accurate enough to detect the difference between logic-high and logic-low voltages on the devices' output pins.

The D/S system on most ICTs consists of a rail driver and a simple comparator. This design is simple and inexpensive, because it consists of readily available off-the-shelf parts. The rail driver typically has an output impedance of approximately 5 ohms and a no-load driver error of approximately 150 millivolts. The sensor usually exhibits greater than 300 millivolts of voltage input error.

More accurate ICTs use a closed-loop, custom ASIC that greatly improves the accuracy of the driver and sensor pins. These testers cost more and require greater engineering effort, but they typically have much lower output impedance (1 ohm or less) and smaller D/S error (100 millivolts or less).

Either D/S system can adequately test devices that operate at more than 1.2 volts under no-load current conditions. However, it may be impossible for simple D/S systems to test devices that operate at less than 1.2 volts, due to inherent inaccuracies in the pin sensors. Even higher voltage devices may be untestable with simple D/S systems under backdriving conditions, because of the high output impedance of the rail driver pins.

Accuracy and Backdriving

Backdriving occurs whenever a pin driver needs to supply current to temporarily overdrive a component output that is in the logic state opposite to what the pin driver is trying to achieve. Backdriving is common and can occur due to the circuit design, board faults or missing isolation code in the test program.

How common is backdriving? An analysis of an ICT program for a PC motherboard found that backdriving occurred during 17 of 56 digital device tests. In addition, a total of 156 backdriving events required more than 50 milliamperes of current. The median backdrive current was 176 milliamperes. The highest current recorded for a backdrive event was 600 milliamperes. The longest time for a backdrive event was 2.5 milliseconds.

Backdriving of this magnitude can be problematic on ICTs that use high output impedance rail drivers. This is because the voltage inaccuracy of the pin driver increases dramatically as backdriving current increases. At 100 milliamperes of backdrive current, the driver is no longer accurate enough to test 1.2-volt devices. At 200 milliamperes of backdrive current, the driver can no longer accurately test 3.3-volt devices. When backdrive current exceeds 300 milliamperes, the driver is not even accurate enough to test 5-volt devices. At 500 milliamperes of backdrive current, the high output impedance driver exhibits more than 2 volts of error. In contrast, an ICT with a low output impedance driver is accurate enough to test 0.8-volt devices, even at backdrive currents of 400 milliamperes.

If the ICT's D/S pins are not accurate enough to drive and sense pins on low-voltage devices, electronics assemblers may decide not to test those components. Or, they can use an alternative unpowered, vectorless test technique, such as analog capacitive opens or diode junction tests. These techniques are inferior to digital vector testing, because they lengthen test times and increase fixture cost and complexity. In addition, they cannot detect if the part is bad or malfunctioning.

Because of the inaccuracy of the D/S system in conventional ICTs, and the shrinking margin of error between high logic and low logic thresholds, there is an increased chance that good low-voltage components will be indicted as bad. False failures increase repair costs and lead to unnecessary rework that could damage the PCB.

Threatened Devices

Because of their small size and low maximum voltage thresholds, low-voltage devices are more susceptible to the following failures.

Gate oxide breakdown. Because low-voltage components have thinner transistor gate oxides, they are more susceptible to damage when exposed to overvoltage. This failure mechanism is known as time-dependent dielectric breakdown, and it is an interaction between time, temperature, voltage and gate oxide width.

Gate oxide breakdown can occur when a device pin is driven to a voltage greater than its maximum specified rating. For example, the maximum specified voltage rating of Intel's FSB/PSB bus is 1.75 volts. If device pins on this bus are driven to voltages greater than 1.75 volts for an extended time, the transistor gate oxide will be damaged.

Most ICTs are designed so that groups of D/S pins share the same logic level assignments. This design is inexpensive, but it can lead to problems when D/S pins in the same group are connected to components with different voltage thresholds. If programmers are forced to use common logic level assignments for all pins in the group, some low-voltage devices could be driven beyond their maximum specified voltage ratings.

Overvoltage is also more likely to occur on ICTs that use high output impedance drivers, because programmers may increase test voltages to compensate for voltage inaccuracies that occur when a pin driver is backdriving.

More sophisticated ICTs avoid these problems. Their D/S pins are more accurate, and their drivers are designed so that logic level thresholds for each pin can be programmed independently. This per-pin programmability prevents devices from being inadvertently driven beyond their maximum voltage ratings, and it ensures that each device pin is driven to its exact logic level threshold.

Electrostatic diode overstress. Diodes that protect against electrostatic discharge (ESD) can fail if they are subjected to backdrive currents beyond a specified maximum. Some device manufacturers recommend that ESD diodes not be overstressed beyond 100 milliamperes of current. Exceeding these ratings can cause damage that goes undetected by factory testing and can be a source of latent failures in the field. Devices with damaged diodes lack protection from ESD. This can degrade the performance of the device and eventually cause a catastrophic failure.

To identify and avoid situations that could overstress ESD diodes, ICTs must be able to measure backdriving current in real-time, report where backdriving is occurring on the PCB, and set limits on maximum backdriving current and time.

CMOS latch-up. This failure mechanism occurs when a pair of transistors forms a PNPN or NPNP silicon-controlled rectifier structure. This results in a low-impedance, high-current path from power to ground in the device, which can cause the device to malfunction or be permanently destroyed. Latch-up is usually induced by a sudden increase or decrease in voltage applied to the inputs of the CMOS device. This can occur due to ESD or during a test, when an output suddenly changes its logic state while it is backdriven.

To prevent voltage spikes from occurring during testing, multilevel digital isolation techniques are required. These techniques ensure that all outputs on a net are controlled and in a known state prior to connecting the digital driver. Some ICTs only isolate outputs that are directly connected to the inputs of the device under test. However, this will not prevent voltage spikes on nets that are not directly connected to the device under test.

Test duration. Current flowing through a backdriven component increases the temperature of the component's output junction and bond wires. The maximum time that an IC can be safely backdriven depends on the number of pins that are backdriven, the current level, test duration, packaging and technology. Long backdrive times may cause bond wires to fail if the temperature of the wire rises above its melting point. Long backdrive times could also activate a fatigue mechanism in the wire that can cause latent defects and early component failure.

Therefore, it's important that ICTs minimize test duration whenever backdriving is occurring. Some ICTs have special digital controllers and memory-behind-the-pin architectures that can apply test vectors quickly and with precise timing. Less sophisticated testers require longer test times, because test vectors are transferred from PC memory during the test. Timing for these testers is unpredictable, because it depends on the type of PC being used, the amount of data being transferred, and whatever else may be running on the PC.

An experiment to compare the two approaches demonstrated that a conventional ICT required 520 times longer to execute 1,000 test vectors than an ICT with a special digital controller (104 milliseconds vs. 0.2 millisecond). Shorter test times put less stress on backdriven components and decrease the opportunity for voltage spikes related to onboard activity.

Safe Testing

To accurately, safely and reliably test PCBs with low-voltage devices, manufacturers should look for ICTs with the following capabilities:

Closed-loop, low output impedance drivers. ICTs should have a driver accuracy below 100 millivolts and an output impedance of less than 1 ohm. This will guarantee the driver can test devices with operating voltages as low as 0.8 volt. It will also ensure that the driver is accurate under no-load and backdrive conditions.

Accurate sensor resolution. ICTs should have a voltage input error of less than 100 millivolts. This will allow the tester to distinguish between high and low logic outputs for devices with operating voltages below 1.2 volts.

Real-time backdrive current measurement. Test drivers should be able to perform real-time measurements of backdrive currents and duration. This feature allows the tester to identify test conditions that require unusually large backdrive currents. It also highlights areas of the test program that have missing or inadequate steps for isolating devices.

Programmable backdrive currents and duration. Programmers should be able to set the maximum backdrive current and time for each device pin during a test. This will protect sensitive devices from being overstressed when there is a fault condition on the board. This feature can also be used to identify faults that are not normally detected by conventional ICTs, such as faulty enable pins and marginal output transistors.

Per-pin programmable logic level assignments. D/S pins should allow individual, rather than group, programming of logic level thresholds, backdrive limits and slew rates. Per-pin programmability allows engineers to assign logic levels that are appropriate for each pin on the device.

Specialized digital controller and timing. ICTs should have dedicated digital controller hardware that can quickly execute digital test vectors with consistent and repeatable timing. ICTs with specialized digital controllers provide faster test times, less backdriving stress and more repeatable test results.

Multilevel digital isolation. ICTs should have test generation and circuit analysis software that automatically disables or inhibits any outputs on the PCB that are connected to nets that are being driven. This capability is critical for avoiding potentially harmful voltage spikes that occur when an output being backdriven suddenly changes its logic state.